Semiconductor chips are typically fabricated in wafer form. Using well known semiconductor fabrication techniques, a wafer undergoes a series of processing steps, such as deposition, masking, etching, implanting, doping, metallization, etc. to form complex integrated circuits on individual dice on the wafer. Currently, several hundred or even thousands of dice may be fabricated on a single wafer.
Semiconductor vendors want to make sure the devices they sell are operational before shipping the product to a customer. The customer expects the product to be not only operational upon receipt, but also will not fail in the field or operate outside of specifications in extreme conditions, such as severe heat or cold. Accordingly, after a wafer is fabricated, the individual die will undergo a number of tests. Initially, while still in wafer form, the individual dice will be electrically tested using a probe. Non-operational dice are marked with an ink and mapped. After the wafer is singulated, the bad dice are discarded while the good dice are packaged. Lead frames are commonly used in the packaging of semiconductor dice. With this type of packaging procedure, the die is placed onto a lead frame, wire bonded, and then encapsulated in a molding material.
Wiring bonding involves the “stitching” of a thin conductive wire, such as gold, between a contact pad on the die and the lead finger of the lead frame. To form a wire bond, a bonding machine forms a small ball at the end of the wire. The ball is then placed in contact with the pad. A combination of heat, pressure, and vibration causes a bond to form between the ball and the pad. A similar process is typically formed between the other end of the wire and the lead frame finger, thereby forming an electrical connection between the pad on the integrated circuit and the lead frame finger. On a typical die, the stitching process is repeated for each pad and lead frame finger pair of the package.
While the formation of wire bonds has been practiced for a long time in the semiconductor industry, the process is still plagued with a number of problems. Often a poor wire bond will be formed at the junction of the bond pad and the ball at the end of the wire for a number of reasons. The stitching machine may misalign the position of the ball relative to the pad, resulting in a poor bond. Other problems may also result if too much pressure is applied during the stitching process, causing damage to the underlying silicon, if or too little pressure is applied, resulting in a poor connection. Similar problems of misalignment, too much, or too little pressure, can also occur on the connection between the lead frame and the wire. In addition, contaminants on the lead frame can also result in the formation of a poor bond between the lead frame finger and wire.
Problems may also occur with the wires themselves. Due to poor integrity, the wires may break. The wires can also be damaged during the mold encapsulation process. During the encapsulation process, a lead frame with a number of die attached thereon is placed into a mold. Molding material in liquid form is then injected into the mold under pressure. During the injection process, the wires may be adversely affected, damaging the integrity of the electrical connections or causing the wire bonds to touch one another. Also during the curing of the molding material, pressure is exerted onto the wires, which may cause the wires to break, tear off at either the bond pad or lead frame, or contact one another.
Given all the potential problems with the wire bond process, many semiconductor companies have developed tests to visually and electrically test the integrity of the wire bonds of semiconductor chips. For example, after a die has been encapsulated, it will often be exposed to an X-ray. The X-ray image allows a visual inspection of wire bonds of the package. The problem with X-rays is that the image is not always clear, and the manual process of inspecting the devices is slow and imprecise. In a known electrical test method, individual signal pins on the device are checked by making use of the existing ESD circuitry on the device. A small amount of current is provided “backwards” to a VSS pin adjacent the signal pin. The current is used to forward bias the diode coupled between the signal pin and the VSS pin. If a current is detected at the signal pin, it indicates that the bond wire is intact and operative.
Complex semiconductor chips often have hundreds if not thousands of pins. Of these, approximately ten to thirty percent are dedicated to provide power to the circuitry on the chip. Power is provided to the chip through a plurality of pins. The power is then typically distributed throughout a chip using several power distribution grids. On a given chip for example, there will typically be a separate distribution grid for core ground (VSS), core power (VDD), Input/Output ground (VSS I/O), and Input/Output power (VDD I/O), each having a plurality of pins to provide power to the grids respectively. For example, the National Semiconductor NDV8611 DVD processor chip has eight (8) core ground (VSS) pins, eight (8) core power (VDD) pins, nineteen (19) VSS I/O pins, and nineteen (19) VDD I/O pins. The remaining pins on the device are signal pins.
Currently there is no known way to electrically test the integrity of individual power and ground pins on a semiconductor device. A method and apparatus for testing individual power and ground pins on a semiconductor integrated circuit is therefore needed.